Dynomotion

Group: DynoMotion Message: 599 From: Azd M Date: 8/23/2010
Subject: What is the maximum sampling frequency of the Kanalog ADCs
Hi All,
I am trying to use ADC6 and ADC7 of the Kanalog board to measure a differential analog signals through a multiplexer (ADG407). I noticed that I need at least 3 cycles on Kflop (270microsecionds) to measure the actual signals of one channel. this raises the question of what is the sampling frequency of the Kanalog ADCs?
the program structure I used is something like this
/===
Wait for next cycle
change the digital gates of the Mux
wait for next cycle 1
wait for next cycle 2
wait for next cycle 3
read ADCs
print the results
loop

/==

Any reduction will effect the accuracy of the measurement.

Regards
Azeddien
Group: DynoMotion Message: 600 From: Tom Kerekes Date: 8/23/2010
Subject: Re: What is the maximum sampling frequency of the Kanalog ADCs
Hi Azeddien,
 
All 8 Kanalog ADCs convert every servo sample cycle (90us).  There is also a low pass RC filter on the inputs (Tau = 100us) so this is probably your main limitation.  Also the Kanalog outputs only update every servo sample period (so if you use an output directly from KFlop to control your mux you may save one sample time delay).
 
Kanalog JP12 exposes the 4 of the Raw ADC 0-3V inputs as pins IN0-IN3.  If you are able to drive those pins directly with a low impedance source you can bypass the low pass filter.  The input circuit is basically a 0.01uF load.
 
Regards
TK